SUBJECT: Ph.D. Dissertation Defense
BY: Jin Yang
TIME: Tuesday, July 15, 2008, 3:00 p.m.
PLACE: MARC Building, 331
TITLE: Quality Inspection and Reliability Study of Solder Bumps in Packaged Electronic Devices: Using Laser Ultrasound and Finite Element Method
COMMITTEE: Dr. I. Charles Ume, Chair (ME)
Dr. Steven Danyluk (ME)
Dr. Suresh K. Sitaraman (ME)
Dr. Jye-Chyi (JC) Lu (ISyE)
Dr. Thomas E. Michaels (ECE)
Dr. Deepak Goyal (Intel)


The transition from traditional through-hole assembly to surface mount assembly is a significant step in evolution of electronic packaging. The use of surface mount devices has helped to decrease size of electronic packages through use of solder bumps between devices and substrates/PWBs. Common manufacturing defects-such as open, cracked, missing, and misaligned solder bumps–are difficult to detect because solder bumps are hidden between device and substrate/PWB. Quality inspection of solder bumps has been a crucial process. Current techniques available for inspecting solder bumps include: 1)electrical testing 2)X-Ray inspection and 3)thermal inspection 4)acoustic inspection. They do not necessarily encompass all capabilities for evaluating quality of solder bumps. The laser ultrasound inspection system under development aims to provide a noncontact, nondestructive, and low-cost solution that can overcome some limitations of current inspection techniques. Main contributions of this thesis work include: 1) Developed new signal-processing methods for analyzing transient signals to improve inspection accuracy and sensitivity, inclduing wavelet analysis and local temporal coherence analysis, 2) Developed an integrated analytical, numerical, and experimental modal analyses approach to predict modal behavior and defect effects on structural characteristics of PEDs, 3) Developed an FE model for predicting presence of defects in thermomechanical reliability study of FCPs 4) Carried out systematic study on the thermomechanical reliability of board-level solder bumps in LGA packages and first-level solder bumps in FCPs with LUII technique and FE method, 5) Expanded application scope of new technique to test vehicles with different package formats and defect types.