SUBJECT: Ph.D. Dissertation Defense
BY: Sungbum Kang
TIME: Monday, April 20, 2015, 2:00 p.m.
PLACE: MARC Building, 201
TITLE: Digital Fringe Projection System for Measuring Warpage of Painted and Unpainted PBGAs and Boards and FEA Studies of PBGA Warpage
COMMITTEE: Dr. I. Charles Ume, Chair (ME)
Dr. Suresh K. Sitaraman (ME)
Dr. Thomas E Michaels (ECE)
Dr. Jianjun Shi (ISyE)
Dr. Michael Mello (Caltech)


Improvements in chip package technologies have led to smaller package sizes and higher density circuitry that require superior reliability of chip packages. One of the crucial factors affecting the reliability of chip packages is warpage which primarily occurs during the reflow process. Because warpage may cause serious reliability problems such as solder bump failure and die cracking, warpage control has become a crucial task. Advancements in warpage measurement and prediction would provide important steps toward addressing this concern. Among the various warpage measurement techniques, fringe projection techniques (i.e., laser fringe projection (LFP) and digital fringe projection (DFP)) have emerged as recent trends due to their non-contact, full-field, and high-resolution (for small viewing area) capabilities for measuring the warpage of chip packages and boards (i.e., printed wiring boards (PWBs) and PWB assemblies). The objectives of this research are to: 1) to improve the measurement capabilities of the LFP system by reducing its laser speckle noise and post-processing time, 2) to develop a DFP system for measuring the warpage of painted and unpainted chip packages and boards, 3) to assess the effects of solder bump pitch, package size, and molding compound and substrate thicknesses on warpage of plastic ball grid array packages by parametric finite element studies, 4) to develop a guideline that manufacturing engineers can use for selecting the most suitable warpage measurement technique for their particular application. The results of this study will help to improve the yields and reliability of chip packages and boards, reduce the manufacturing costs and time to market for chip packages and boards and ultimately reduce the prices of end-products.