SUMMARY

With continued reduction in feature size in microelectronics and with hundreds of millions to more than a billion transistors on a chip, on-chip interconnection has become a challenge in terms of processing, electrical, thermal, and mechanical perspective. Today’s high-performance chips have on-chip back-end-of-line (BEOL) copper traces and vias interspersed with low-k dielectric materials having thicknesses ranging from 30 nm to 1000 nm. In such BEOL stacks, cracking and/or delamination is becoming a common failure mode due to low-strength dielectric materials as well as due to high thermally-induced stresses. However, existing literature has not adequately addressed such failure modes especially because of inadequate mechanical characterization of the low-k low-strength dielectric materials as well as due to the difficulty associated with modeling the vast on-chip network of traces, vias, and dielectric materials through traditional fracture mechanics techniques.
The objective of this thesis is to study on-chip BEOL failures under flip-chip assembly through the development of cohesive zone model as well as through traditional fracture tests and innovative nanoindenter-based shear tests. Starting with four-point and double-cantilever beam (DCB) tests, this work has characterized real-life Cu/low-k stacks under a wide range of mode mixity, and used such experimental results to develop cohesive-zone parameters. The developed cohesive zone parameters are then placed in the BEOL stack to determine the fractured region using 2D and 3D models. The results obtained through cohesive zone model are compared against traditional fracture models as well as experimental failure-analysis data. In addition, nanoindenter-based shear has been developed that can address different mode mixities compared to DCB and four-point bend tests, can determine local BEOL fracture characteristics, and mimic flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.