SUMMARY

The international technology roadmap for semiconductors (ITRS) 2011 report foresees porous dielectric materials as the solution to achieving materials with a dielectric constant of less than 2. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high performance flip-chip packages is to create a reliable die to organic substrate assembly which induces little stresses on the package to prevent a cracking or delamination of the dielectric material.

A class of potential solutions that meet this challenge are MEMS-like compliant freestanding micro-structures used as interconnects. These structures are designed to work as spring-like elements which allow the free lateral motion between a silicon die and its package substrate under thermal or power cycling. The focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges.

The proposed interconnect is scalable and of multiple electrical paths which will provide redundancy. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. The thermo-mechanical reliability of compliant interconnects is also demonstrated.