SUMMARY

With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermo-mechanical reliability is still in infancy. This work explores the thermo-mechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with two-die stacks, this work studies the failure mechanisms in multi-die stacks. These failure mechanisms include dielectric cracking and interlayer dielectric/copper delamination. These failure mechanisms will be investigated through fracture mechanics. Silicon wafers with TSVs are designed and fabricated and subjected to thermal excursions. Cross-sectional SEM failure analysis is carried out to validate the theoretical predictions. In addition, local strain fields under thermal excursions are studied through techniques such as micro-scale Digital Image Correlation (DIC) and/or synchrotron X-ray diffraction. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermo-mechanical reliability of TSVs used in next-generation 3D microelectronic packages.