SUMMARY

The growing demands for cost reduction, miniaturization, and high performance in electronics devices have motivated improvements in the electronic packaging industry. For instance, an area array interconnect was invented to meet the demands of the electronics packaging industry to replace wire bonding or Tape Automated Bonding. Such conventional bonding technology was not compatible with area array interconnect, therefore a new methodology such as Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. In addition, the increasing demand for high performance FCIP is driving I/O counts from 1,000 to 5,000 and bumping pitches down to 100 um. Such challenges push conventional capillary flow underfill processing beyond its processing limits and the conventional process was replaced by no-flow assembly processes. However, the high assembly yield of FCIP with no-flow underfill as a result high I/O counts coupled with finer pitch area array interconnect structures has narrowed the feasible process conditions. In general, a high yield assembly process can be achieved with high values of reflow process design parameters, while high values can cause a large number of voids in FCIP by product. A large number of voids found among solder interconnects in FCIP can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Besides, these can severely reduce reliability. Nevertheless, existing research does not to provide a general answer to the cause of void formation in FCIP. Therefore, the theoretical models will be established to predict the number and to explain the behavior of voids in the FCIP with high I/O density and fine-pitch. Finally, these models will provide a relation between parameters to achieve a high yield and to minimize voids in FCIP using no-flow underfill.