SUMMARY

In their ITRS roadmap the Semiconductor Industry Association projects that by the year 2015 the IC feature size will shrink to 10 nm, and thus, the off-chip interconnects will need to have an area-array pitch of 70um. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, this research aims to develop a unique parallel-path approach which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It will also provide for redundancy and thus result in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, this research aims to develop a variable compliance approach so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work will develop a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigate key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches will be demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed are generic in nature and can be extended to other aspects of electronic packaging.