The Woodruff School

SUMMARY

While 3D stacked multi-processor technology offers the potential for significant computing advantages, these architectures also face the significant challenge of small, localized hotspots with very large power dissipation due to the placement of asymmetric cores, heterogeneous devices and performance driven layouts. In this thesis, a new thermal management solution is proposed that seeks to maximize the performance of microprocessors with dynamically managed power profiles. To mitigate the non-uniformities in chip temperature profiles resulting from the dynamic power maps, phase change materials (PCMs) with an embedded heat spreader network are strategically positioned near localized hotspots, resulting in a large increase in the local thermal capacitance in these problematic areas. Theoretical analysis shows that this results in an up-to-twenty-fold increase in the time that a thermally constrained core can operate before a power gating or core migration event is required. Coupled to the PCMs are solid state coolers (SSCs) that serve as a means for fast regeneration of the PCMs during the cool down periods associated with throttling events. Using this combined PCM/SSC approach allows for devices that operate with desirable the combination of low throttling frequency and large overall core duty cycles, thus maximizing computational throughput. Complementary to theoretical characterization of the proposed thermal solution, a prototype device called a �Composite Thermal Capacitor (CTC)� that monolithically integrates micro heaters, PCMs and a spreader matrix into a Si test chip will be fabricated and tested to validate the efficacy of the concept. Furthermore, a thermoelectric cooler and vertical nanopillars integrated into the CTC will be investigated experimentally to quantify their ability to enhance the energy storage and removal rates from the device. Finally, a combined electro-thermal model will be developed to quantify the impact of the proposed thermal solution on the computational throughput of many core microprocessors.

SUBJECT:	Ph.D. Proposal Presentation

BY:	Craig Green

TIME:	Friday, May 13, 2011, 2:15 p.m.

PLACE:	Love Building, 210

TITLE:	Composite Thermal Capacitors for Transient Thermal Management of Multicore Microprocessors

COMMITTEE:	Dr. Andrei Fedorov, Co-Chair (ME) Dr. Yogendra Joshi, Co-Chair (ME) Dr. Baratunde Cola (ME) Dr. Sudhakar Yalamanchili (ECE) Dr. Muhannad Bakir (ECE)

SUMMARY While 3D stacked multi-processor technology offers the potential for significant computing advantages, these architectures also face the significant challenge of small, localized hotspots with very large power dissipation due to the placement of asymmetric cores, heterogeneous devices and performance driven layouts. In this thesis, a new thermal management solution is proposed that seeks to maximize the performance of microprocessors with dynamically managed power profiles. To mitigate the non-uniformities in chip temperature profiles resulting from the dynamic power maps, phase change materials (PCMs) with an embedded heat spreader network are strategically positioned near localized hotspots, resulting in a large increase in the local thermal capacitance in these problematic areas. Theoretical analysis shows that this results in an up-to-twenty-fold increase in the time that a thermally constrained core can operate before a power gating or core migration event is required. Coupled to the PCMs are solid state coolers (SSCs) that serve as a means for fast regeneration of the PCMs during the cool down periods associated with throttling events. Using this combined PCM/SSC approach allows for devices that operate with desirable the combination of low throttling frequency and large overall core duty cycles, thus maximizing computational throughput. Complementary to theoretical characterization of the proposed thermal solution, a prototype device called a �Composite Thermal Capacitor (CTC)� that monolithically integrates micro heaters, PCMs and a spreader matrix into a Si test chip will be fabricated and tested to validate the efficacy of the concept. Furthermore, a thermoelectric cooler and vertical nanopillars integrated into the CTC will be investigated experimentally to quantify their ability to enhance the energy storage and removal rates from the device. Finally, a combined electro-thermal model will be developed to quantify the impact of the proposed thermal solution on the computational throughput of many core microprocessors.