SUBJECT: Ph.D. Proposal Presentation
   
BY: Nicholas Ginga
   
TIME: Wednesday, December 12, 2012, 1:30 p.m.
   
PLACE: MARC Building, 201
   
TITLE: On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects
   
COMMITTEE: Dr. Suresh K. Sitaraman, Chair (ME)
Dr. Kyriaki Kalaitzidou (ME)
Dr. Richard W. Neu (ME)
Dr. Z.L. Wang (MSE)
Dr. W. Jud Ready (GTRI/MSE)
 

SUMMARY

ABSTRACT
The cohesive fracture of thin films is a concern for the reliability of many devices in microelectronics, MEMS, photovoltaics, and other applications. In microelectronic packaging the cohesive fracture toughness has become a concern with new low-k dielectric materials currently being used. To obtain the low-k values needed to meet electrical performance goals, the mechanical strength of the material has decreased. This has resulted in cohesive cracks occurring in the Back End of Line (BEoL) dielectric layers of the microelectronic packages. These cracks lead to electronic failures and occur after thermal loading (due to CTE mismatch of materials) and mechanical loading. To prevent these cohesive cracks, it is necessary to measure the cohesive fracture toughness of these thin films to implement during the design and analysis process. Many of the current tests to measure the cohesive fracture toughness of thin films are based on methods developed for larger scale specimens. These methods can be difficult to apply to thin films due to their size and require mechanical fixturing, physical contact near the crack tip, and complicated stress fields. Therefore, a fixtureless cohesive fracture toughness measurement technique has been developed that utilizes photolithography fabrication processes. This technique uses a Superlayer thin film with a high intrinsic stress deposited on top of the desired test material to drive cohesive fracture through the thickness of test material. In addition to developing a technique to measure the fracture toughness of dielectric thin films, the use of carbon nanotube (CNT) forests as off-chip interconnects is investigated as a potential method to mitigate the fracture of these materials. The compressive and tensile modulus of CNT forests is characterized, and it is seen that the modulus is several orders of magnitude less than that of a single straight CNT. The low-modulus CNT forest will help mechanically decouple the chip from the board and reduce stress occurring in the dielectric layers as compared to the current technology of solder ball interconnects and therefore improve reliability.