SUBJECT: Ph.D. Proposal Presentation
BY: Wei Chen
TIME: Tuesday, September 9, 2014, 2:00 p.m.
PLACE: MARC Building, 201
TITLE: Design, Fabrication, and Reliability Study of Second-Level Compliant Microelectronic Interconnects
COMMITTEE: Dr. Suresh K. Sitaraman, Chair (ME)
Dr. F. Levent Degertekin (ME)
Dr. Aldo A. Ferri (ME)
Dr. Azad J Naeemi (ECE)
Dr. Rao R Tummala (ECE)


Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect reliability. The geometry of the compliant interconnect, its dimensions, and the material and processes used for fabricating the interconnect influence its mechanical and electrical characteristics, fabrication and assembly yield, thermo-mechanical and drop/impact reliability, and cost of fabrication. Although studies have examined various compliant interconnect designs, a multi-objective and multi-physics design optimization of the compliant interconnect has not been adequately pursued and implemented in prototypes. The first objective of this thesis is to systematically examine various design parameters that influence the mechanical and electrical characteristics of a multi-path interconnect, and to develop an interconnect design that will meet mechanical and electrical requirements of microelectronic systems. The second objective of this thesis is to develop a dry-film based sequential processes to fabricate an area array of compliant interconnects on a silicon wafer, and to singulate and assemble the silicon substrate on an organic printed circuit board with the compliant interconnects as second-level interconnects. In particular, in this work, an array of about 45 45 interconnects on an 18 18 mm silicon substrate are assembled on an organic board. The fabricated interconnects have a footprint of 280 m, an arcuate beam width of 10-20 m, an arcuate height of 17-22 m, and a pitch of 400 m. The third objective of this work is to determine the reliability of the assembly under thermal cycling and drop test conditions. The results from such tests are then used to validate the simulation models and to further enhance the interconnect design. It is demonstrated in this work that the compliant interconnects can effectively isolate the silicon substrate from the board under thermal as well as mechanical loading conditions, and will likely to result in reduced stresses in the silicon substrate.