SUMMARY

Major challenges in maintaining quality and reliability in today’s microelectronics devices come from the ever increasing level of integration in the device fabrication, as well as the high level of current densities that are carried through the microchip during operation. In order to develop a framework for design and reliability assessment, it is imperative to develop a predictive capability for the thermal response of micro-electronic components. In the first part of this dissertation, a computationally efficient and accurate multi-scale reduced order transient thermal modeling methodology was developed using a combination of two different approaches: “Progressive Zoom-in” method and “Proper Orthogonal Decomposition (POD)” technique. The capability of this approach in handling several decades of length scale from “package” to “chip components” at a considerably lower computational cost, while maintaining satisfactory accuracy was demonstrated. The second part of this research is an experimental study of rapid transient Joule heating in three dimensional chip interconnect architectures. A set of 100-nanometer-thick Cu interconnects buried in low-k dielectric materials were designed and fabricated. To measure the transient temperature distribution in the Cu-interconnects, a set of imbedded sub-micron resistance thermometers on top of the interconnect layer with a 300 nanometer barrier layer of silicon dioxide were fabricated. The objective of this study is to experimentally examine the effect of rapid transient power input profiles with different amplitudes and frequencies in Cu interconnects, and compare them with the modeling framework. Additionally, the size effect on the thermal and material properties of Cu interconnects will be explored and verified through further device fabrication and data comparison with numerical models.