SUBJECT: M.S. Thesis Presentation
BY: Philip Chung
TIME: Wednesday, April 19, 2017, 9:00 a.m.
PLACE: MARC Building, 401
TITLE: Vibration Analysis of Electroplated Copper Compliant Interconnects
COMMITTEE: Dr. Suresh K. Sitaraman, Chair (ME)
Dr. Richard W. Neu (ME)
Dr. Vanessa Smet (ECE)


Microelectronic packaging interconnects are subjected to mechanical damage due to thermal and power cycles, drop impact shock, and various vibration loads during application. As traditional microelectronic packaging interconnects are rigid, compliant interconnects are being pursued to facilitate more independent deformation between the substrate and the die while experiencing lower stress and strain, thus improving the overall mechanical reliability. However, though there have been studies that examine these interconnects under thermal fatigue and drop testing, the literature on vibration loading is scarce.

This thesis characterizes the response of a compliant microelectronic packaging interconnect under random vibration loading and develops an assembly process flow that produces the most reliable bonded structures for testing. The interconnect used in the study is a 3-arc electroplated copper structure that serves as the Second-Level packaging interconnect. Random vibration loading is selected instead of sine sweep loading, as it produces a more realistic simulation of the conditions during application. A power spectral density spectrum analysis is used to calculate the stresses experienced under such fatigue loading through finite-element simulations. In parallel, silicon dies with compliant interconnects are assembled on organic substrates, and experimental vibration testing is conducted to determine the interconnect fatigue life. Based on simulations and experiments, a high cycle fatigue prediction methodology is developed for the compliant interconnect that can be employed for future design and analysis of compliant interconnects for various applications.