|SUBJECT:||M.S. Thesis Presentation|
|TIME:||Tuesday, July 18, 2017, 12:00 p.m.|
|PLACE:||Love Building, 210|
|TITLE:||Single-Phase Liquid Cooling for Thermal Management of Power Electronic Devices|
|COMMITTEE:||Dr. Samuel Graham, Chair (ME)
Dr. Cassandra Telenko (ME)
Dr. Vanessa Smet (ECE)
Power electronic devices such as MOSFETs, HEMTs, and IGBTs often face reliability challenges due to poor thermal management during device operation at high power densities. In the conventional approach, such devices are packaged on power electronic substrates (e.g., direct bonded copper or DBC) which is then attached to heat spreaders and ultimately cold plates to remove dissipated thermal energy. Thus, there are several critical layers that add to the thermal resistance of the overall design that limit the thermal management of power electronic devices. By eliminating layers, the integration of liquid cooling techniques has shown promise to significantly reduce (up to 2.3x) the thermal resistance in power electronic cooling systems as compared to the thermal resistance found using a conventional cold plate cooler design. Thus, the main objective of this work is to evaluate vertical (jet impingement) and horizontal (microchannel) cooling schemes with integrated cooling on the backside of the DBC substrate. The cooling systems in this work utilize direct integration of cooling electronics (DICE) techniques with enhanced heat transfer through microstructural features integrated into the DBC. For this work, each cooling method underwent a pseudo-optimization design analysis to identify the relevant contributors to the performance of the heat sink designs. Parameters such as pressure drop, pumping power, and heat transfer coefficient were used to assess industry and manufacturing tradeoffs associated with each design. Through experiments, the pressure drop, chip junction temperature, and inlet and outlet temperatures were measured and will be presented. To validate the experimental results, numerical and analytical models were developed to simulate the experimental environment and will be presented. Finally, the prospects for integrating these techniques into real power electronic packaging architectures will be discussed.